Apparatus for detecting and localizing malfunctions in electronic devices



Feb. 22, 1966 Filed Dec. 30, 1960 MALFUNGTIONS IN ELECTRONIC DEVICES L.C. HIGBY, JR APPARATUS FOR DETECTING AND LOCALIZING COMPARATOR 2Sheets-Sheet 1 INVENTOR LEONARD C. HIGBY, JR.

FIG. 1

SIGNAL M0 ONE 7 REGISTER GENERATOR ZERQ 7 CHECK REGISTER t0 t1 t2 t3 t45 E ,CP! j j 0P2 n 0P5 J j W n 0P5 j 0P6 g FIG. 4

CHECK REGISTER I/EXCLUSIVE-OR A0 42 44 'AND I g i AND IIAND-ilNDMHNGMEANS w 1 5 a C01? fs fi ATTORNEY United States Patent APPARATUS FORDETECTING AND LOCALIZTNG MALFUNCTIONS IN ELECTRONIC DEVICES Leonard C.Higby, .l'r., Endicott, N.Y., assignor to International BusinessMachines Corporation, New York,

N.Y., a corporation of New York Filed Dec. 30, 1960, Ser. No. 79,782 4Claims. (Cl. 340-1461) The present invention relates generally toelectronic data processing equipment and in particular to a novel systemfor detecting and localizing failures in such equipment.

Present day data processing equipment, such as computers for example,are extremely complex apparatus composed of a number of building blockunits each of which consists of a great variety and number of differentelectrical components. As a result of this involved nature, if amalfunction arises or if complete inoperability results, it has beenvery difficult heretofore to determine precisely which part of the totalapparatus is not working properly in order that it may either bereplaced entirely, or itself examined to determine which component orcomponents must be repaired or replaced to make it operable. Forexample, although a particular malfunction may be finally attributeddirectly to the failure of but a single resistor, capacitor or othersuch component which could be replaced quickly and relativelyinexpensively, the time and effort which had to be expended in order todetermine even in which portion of the apparatus the defective componentwas located was frequently considerable.

Obviously, during those periods while a computer is being repaired it isunavailable for use. This not only can be costly in a commercialproduction operation, but also can have disastrous effects in a casewhere a computer is closely integrated into the operation of an aircraftor missile, for example. Thus, whereas in a ground installation, faultyequipment can be removed and replaced in toto, in an aircraft such aprocedure is obviously out of the question and failure while the craftis airborne can be disastrous for the mission of the aircraft and/ orresult in great danger to its occupants.

Additionally, the degree of ditliculty associated with this phase ofmaintenance strongly influences other facets of the over-allmaintainability picture, such as replacement parts, logistics, personnelrequirements and test equipment needed, among other things. In fact,these fatcors may be of critical importance in regard to aircraft ormissiles where weight and space requirements are at a premium.

It is, therefore, a primary object of the invention to provide a dataprocessing equipment failure location system which is incorporated as anintegral part of the equipment.

Another object of the invention is to provide a system for testingdifferent functional units of a data processing apparatus independentlyand indicating the location of a failure Within such units.

A still further object of the invention is to provide a system forrepetitively and rapidly testing data processing apparatus functionalunits to detect and locate intermittent failures. I

Briefly, the invention contemplates the provision of signal generatingmeans for producing coded signals corresponding to pairs of binary testwords, each pair consisting of an inquiry word and a response word. Theinquiry word containing known binary information is presented to a unitto be tested and the output of the unit is converted to the binarycomplement of the inquiry word and stored. The response word containinginformation that is the binary complement of the inquiry word issimilarly stored. Both sets of stored information are fed into a comparecircuit where they are compared bit for bit.

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If any position, or bit, of one of the compared words is in disagreementWith the corresponding bit in the other compared word, an error signalis produced indicating which position of the word is in error therebylocating both the particular malfunctioning apparatus and the specificpart of the apparatus that is operating improperly.

The foregoing and other objects, features and advantages that will beapparent from the following more particular description of a preferredembodiment of the invention as illustrated in the accompanying drawings.

In the drawings:

FIG. 1 is a diagrammatic representation of a system constructed inaccordance with this invention;

FIG. 2 illustrates a preferred embodiment of the apparatus of theinvention;

FIG. 3 is a graph of the timing control pulses used with the apparatusof FIG. 2; and

FIG. 4 shows a preferred form of compare circuit for use in theinvention.

With reference especially to FIG. 1, an examination of the moregeneralized structure and requirements of each of the major functionalunits will be entered into at this time.

SIGNAL GENERATOR In addition to conventional operational data, this unitfor present purposes contains a special set of coded test signalscorresponding to one or more pairs of binary Words, where each pairincludes an inquiry word and a response word, and the response word of agiven pair is the binary complement of its companion inquiry word.

Further, the test words have a sufficient number of bits so as to enablecomplete simultaneous testing or actuation of all positions of thefunctional units of the equipment being tested. For example, if thearithmetic register of a computer being tested has a total parallelinput capacity of acceptance of 22 bits, then the Words for testing thisregister to its full capacity must also have a 22 bit magnitude.

No one particular type of unit is required for the proper functioning orthe use of the system of the invention. However, in order to performrapid and repetitive testing for the determination and location ofintermittent failures, which is a valuable facet of the invention, it isimportant that the signal generator be able to provide such signalinformation in that manner.

Any of a number of different types of devices meet the aboverequirements such as, for example, magnetic drum storage means, magnetictapes, magnetic disk memories and core memories.

One such a signal generator of the magnetic core type is the memoryelement 21B illustrated in the US. Patent 2,914,248 to Ross et al.

MQ REGISTER This register is a type of storage device normally used forperforming the fundamental arithmetic operations and/or other moresophisticated computations that the equipment is capable of providingand is generally comprised of a plurality of individually settablebistable elements.

As such, this register is conventionally an integral part of dataprocessing equipment or computers and, therefore, does not have to beadded in order to practice the invention. On being properly impulsedfrom the signal generator, the register can provide a first output atOne (1) which is binarily identical to the input word, and a secondoutput available at Zero (0) each bit of which is the binary complementof the corresponding input word.

The memory address register shown in FIG. 24 of the Ross et al. patentand described in detail therein exemplifies a satisfactory register forpresent purposes.

CHECK REGISTER This register can be of the same general construction asthe MQ register or it can be a less sophisticated structure since theability to convert a given input to its binary complement is not arequisite of this register whereas it is for the MQ register.

Such a register can, in many cases, depending on the overall design andstructure of the data processing apparatus, comprise a unit which duringnormal operation of the equipment performs other services as its primaryfunction while also serving in its present capacity during the practiceof the invention.

As to the broad quantitative and functional requirements, this registerhas at least as large parallel word input capacity as the MQ registerand is selectively impulsable to receive, store and read outinformation.

The register of the Ross et al. patent referenced above in regard to theMO register is a full equivalent for this register also.

COMPARATOR The comparator is comprised generally of a plurality ofEXCLUSIVE-OR logic circuits, one for each corre sponding pair of bits inthe inquiry and response Words and having individual and separate inputsand outputs. With such a circuit, the only time an output is obtained iswhen the corresponding paired inputs differ.

The output of each position, i.e., each EXCLUSIVE OR circuit, isoperably connected to a separate indication means, such as a signallight, so that when an error is detected in any .position of the testword, visual indication is obtained of the exact position in which theerror exists. Also, whenever an error signal is so obtained, it is usedto prevent a change in state of the registers thereby maintaining theerror indications in each of the registers.

OPERATION Still referring to FIG. 1, it is assumed that the signalgenerator can provide a plurality of distinct coded signals or words inparallel, i.e., simultaneous read-out from different output positions,and also provide a plurality of these words in a sequence Where thewords differ from one another in a predetermined manner. The essentialcharacteristic of these signals is that they can exist in either one oftwo possible states, i.e., they are binary. We shall term these levelsas O and l realizing that they can refer to different voltage levels,current levels or other suitable distinguishing means.

Although in a preferred embodiment of the invention set forth herein,the test words provided by the generator were actually of 22-bitmagnitude, for simplicity in the following description it is assumedthat the test words and the capacity of the units tested are all of4-bit magnitudes.

First, a 4-bit inquiry word (1111 for example) is read into the MQregister. The register is then impulsed to provide an output at ZERO,i.e., the binary complement of the word, or 0000, and present this tothe check register. Accordingly, the MQ register now contains a settingof 1111 and the check register a setting-of 0000.

The comparator is inhibited from reading out at this time and thereforedoes not now indicate an error signal even though each position of thetwo registers diifer from one another.

With the MQ and check registers continuing to hold 1111 and 0000,respectively, the corresponding response word is obtained from thesignal generator which is the binary complement of the inquiry word, or0000, and read into the MO register. This causes each position of theregister to change from the 1 condition to the condition and store theresponse word 0000. Simultaneously, with the setting up of the responseword in the MQ register, the check register is prevented from reading inthe ZERO output of the MO register and therefore the check registercontinues to hold the word 0000.

pulsed to compare the information from the two registers. If eachposition of the two words agree, i.e., as here the readout from eachregister being 0000, then there is complete agreement and the comparatorwill not indicate an error. However, if there is an error, for examplein the first position, then a signal is made available through the firstposition of the comparator to indicate by a light or other such meansthat this position is in error.

When the comparator notes an error, and thus incorrect operation of aunit being tested, the MQ and check registers are controlled to preventadditional impulsing by information from the signal generator whichwould otherwise remove the error settings in the registers and therebyimpede the taking of corrective measures. Accordingly, the error willstay in the registers and comparator until an affirmative resetting ismade.

SPECIFIC STRUCTURE Turning now to FIGS. 2 and 3 and the detailedstructure of a preferred embodiment of the invention, the signalgenerator is seen to comprise generally a magnetic drum 10 having aspecial portion containing the required test information that forpresent purposes will be considered to include a plurality of pairs ofwords of 4-bit magnitude, each pair consisting of two words binarycomplements of each other and all arrangedrin sequential order. Fourread heads indicated generally at 11 are arranged in operative positionrelative to the drum 10 for individually and simultaneously reading outthe four respective positions of each of the test words. The outputs ofeach of the read heads are fed into separate read amplifiers 12-15 forproviding separate signal pulses of usable magnitude for each bit of thewords read from the drum.

The drum 10 also includes a plurality of timing tracks for generatingclock pulses to provide a correct timing relationship between thevarious functions in general and, in particular, the associatedfunctions of the present test procedure. Thus, for our purposes six (6)clock pulses are generated, CPI-C196, the timing relationship of whichis indicated in FIG. 3.

The MQ register comprises four flip-flops 16-19 which receive theamplified signals from the generator through AND gates (GT) 2043 whichare actuated by CP3. These flip-flops have a One (1) output which isbinarily equivalent to the input signal and a Zero (0) output which isthe binary complement of One. These flip-flops are of the same type setforth in the above mentioned Ross et a1. patent that require resettingbefore impulsing with a signal and which is accomplished here by CPI.

By way of explanation, resetting of the flip-flops of the MQ registerestablishes a 1 status at the Zero output and a 0 status at the Oneoutput. Accordingly, on receiving a 1 input, for example, afterresetting changes the One output to a 1 and the Zero output to a 0. Onthe other hand, if the input signal is a 0 after resetting the outputsremain at the reset condition.

For indicating the difference between pulses and voltage levels, theconvention is adopted in the drawings of illustrating the former byarrowheads and the latter by the diamond symbol.

The check register is of similar construction to the MO register havingfour flip-flops 28-31 fed through gates 32-35, respectively and reset byCP2. These gates are sampled at CP4 time. Signals from the Zero outputof the flip-flops 1619 are fed into the respective gates 32-35.

The comparator is comprised of four separate EX- CLUSIVE-OR circuits36-39 each of which receives one position of the One output of the MOregister and the corresponding output from the check register. Thecomparator is controlled to operate only at CPS time.

Examining the specifics of the EXCLUSIVEOR circuit utilized in thecomparator (FIG. 4), it is seen that the two register outputs are bothintroduced to the input of an AND gate 40 and an OR gate 41. The outputof the OR gate is fed into the input of another AND gate 42 and theoutput of gate 40 is presented to the input of an inverter 43 (I) theoutput of which is also presented to the input of gate 42. When the twoinputs to the gates 40 and 41 are the same, the OR gate output is up forthe gate 42, but since the out-put of gate 40 is up, the output ofinverter 43 is down and gate 42 is not actuated. However, if theEXCLUSIVE-OR inputs are not in agreement, in addition to OR gate 41providing an input to gate 42, the down output of gate 40 is convertedby the inverter to an up condition and gate 42 passes an error signal.At CP5 time such an error signal is gated by an AND gate 44 to theindicating means.

The indicating means includes four separate light sources 45-48 each soadapted as to he actuable by the signal output of one of theEXCLUSIVE-ORs of the comparator.

DETAILED OPERATION For succinctness of expression and clarity ofexplanation, it is assumed that the test set previously set into thedrum consists of a single inquiry word 1111 fol lowed by a response word0000. It is, of course, to be understood that such a test can consist ofany number of pairs of inquiry and response words where the inquirywords can have any predetermined binary configuration. In fact, it isadvisable that the test words he so constructed as to give the worstpattern for the unit being tested.

At t0 time, the registers are reset by CPI and CP2 pulses so that theOne output of each flip-flop is at a 0 level and the Zero output standsat a 1 level.

At t1 times the drum is synchronized such that the inquiry word 1111 isdisposed in opposed relation to the read heads 11 and read off the drumby CP3 pulses sampling gates 20-23. After amplification by the readamplifiers 12-15, the signals pass through gates 20-23 now open. Thegated signals impulse the flip-flops 16-19 to the 1 condition at the Oneoutput and to the 0 state at the Zero output.

At t2, the 0 condition of the Zero output of the MO register ispresented through the gates 32-35 to the input of flip-flops 28-31 ofthe check register. Since the One output of this register has alreadybeen set to a 0 state, there is no change effected in the register atthis time.

Since CPS is not up, there is no comparing performed by the comparatorat this time despite the fact that corresponding positions of the tworegisters are all in disagreement.

At t3 time the MO register is reset as before, i.e., 0 at the One outputand l at the Zero output. Since no CP4 and CPS pulses are present nowthe check register is unaffected by the resetting of the MO register andno comparison takes place.

At t4 time, this permits the response word 0000 on the drum 10 to beread out to pass through gates 20-23 and be presented to the input offlip-flops 16-19. Since the One output of these flip-flops are each atthe reset condition, i.e., 0, there is no change effected in theregister. Also, since CP4 is down, no change in the check register isproduced.

At time each of the EXCLUSlVE-ORs comprising the comparator is madeoperative by CPS pulses. As shown above, if each of the paired inputs tothe comparator is in mutual agreement, no signal is available to theindicating lights 45-48.

If, however, one or more of the paired inputs to the comparator are inmutual disagreement, a signal is available from each of those positionsin error to the corresponding indicating lights.

Simultaneously, with the visual indication of an error, the errorsignals are gated through a multiple input OR gate 49 to the input of aflip-flop 50. The Zero output of this flip-flop is presented to theinputs of AND gates 51-54 so that when the Zero output is in an up levelcondition, these gates permit the clock pules CPI, CP2,

CPS and CP4 to pass and be available to the registers. This up levelcondition of the Zero output can only be obtained by actuation of amanual reset button 55 which causes the flip-flop 50 to reset at t6 timeby CP6 pulses. When an error signal is made available from the OR gate49 to the input of the flip-flop 50, this sets the Zero output to the 0state closing AND gates 51-54 preventing further information being readinto the registers and thereby holding the error information in theregisters. This is an important aspect of the invention in that a meretransitory indication of incorrect operation of a register is of littleuse, whereas fixing the erroneous information in the registers providesthe needed time for observing the apparatus closely and takingappropriate corrective measures.

The error status will continue in the equipment until the manual resetbutton 55 is depressed switching the Zero output of the flip-flop 50once again to the up level enabling gates 51-54 and passing the clockpulses to the registers. Then the procedure will continue as before withthe reading of new test words and comparing their settings in theregisters.

Having established that the MO and check registers are in good operatingcondition as set forth above, it is a further contemplation of theinvention to substitute other registers or such functional units foreither the MO or check registers. Accordingly, by proceeding as before,these new units or registers can be satisfactorily tested and if foundto be operating improperly, the faulty part of the apparatus can belocated. I

Although a single inquiry and response word have been used in the abovedescription, it is considered within the contemplation of the inventionto provide a sequence of inquiry and response words which are readrapidly and repetitively into a unit being tested in order to detect anyintermittent errors which might not show up under just a single orperhaps even several testing operations. This is an important aspect ofthe invention since intermittent errors cannot only adversely affect thecomputer operation to the same degree as a more permanent type offailure, but they are inherently very difficult to detect and locate dueto their infrequent and/ or short-lived occurrence.

Additional beneficial results can be obtained particularly in regard tothe test examination of the check register when the test is conductedwith one or more sets of two special pairs of test words applied insequence. Thus, if the second inquiry word is the full binary complementof the first inquiry word in each set (or in effect identical to thefirst response words), the registers are not only statically placed inboth possible binary states but both possible dynamic changes betweenthe two states are achieved, i.e., 1-0 and 0-1. This enhances thetesting procedure since certain types of malfunctions only occur duringone of the dynamic states and of course would not necessarily bedetected by an examination of one of the static state conditions of aregister.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. A system for localizing inoperability in a device consisting of aplurality of electrical bistable elements having individual inputs towhich information representing signals may be applied for setting theelements to first or second binary information representing states, eachsaid element having true and complement outputs operable to supplyoutput signals representing respectively the binary information state towhich the element is set and the binary complement of that state,comprising:

signal generating means for providing test signals including at leastone inquiry word having a number of bits equal to the number of elementsin the device and a response word which is the binary complement of thecorresponding inquiry word;

means for connecting the signal generating means to the inputs of saiddevice;

register means connected to receive the signals provided by thecomplement outputs of the elements and to provide output signals whichare the binary equivalent thereof; and

bit-for-bit comparing and indicating means operably connected to thetrue outputs of the elements of the device and the outputs of theregister means for comparing corresponding positions of the said twooutputs and indicating those positions having ditfering binary states.

2. An arrangement for detecting malfunctions of a signal storage devicewhich is operable in response to application thereto of a signalrepresenting a binary value for storing said value and supplying uponreadout true and complement signals representing respectively the binaryvalue and its binary complement, comprising:

a signal generator for supplying in time sequence a first signalrepresenting a binary value and a second signal representing the binarycomplement of said value;

means for supplying said first and second signals to said storagedevice;

means operable after application of the first signal to the storagedevice and prior to application of the second signal for reading out thecomplement of the binary value stored in said device;

means operable subsequent to application of the second signal forreading out the binary value stored in said device; and

comparator means for comparing the values read out 8. from said signalstorage device prior to and subsequent to application of the secondsignal and for supplying an error indicating signal in response to onepredetermined result of said comparison.

3. An arrangement as in claim 2, in which the signal generator furtherincludes means for producing the first and second signals repetitivelywhereby intermittent inoperability of the signal storage device isdetected.

4. Apparatus for detecting malfunctions in a signal storage device whichis capable of performing a predetermined logical operation on signalssupplied thereto and References Cited by the Examiner UNITED STATESPATENTS 2,328,750 9/1943 Smith, et al 324-73 3,071,723 1/1963 Gabor340l46.1 X 3,105,955 10/1963 Mauclily 340-146 X ROBERT C. BAILEY,Primary Examiner.

SAMUEL BERNSTEIN, MALCOLM A. MORRISON,

Examiners

1. A SYSTEM FOR LOCALIZING INOPERABILITY IN A DEVICE CONSISTING OF APLURALITY OF ELECTRICAL BISTABLE ELEMENTS HAVING INDIVIDUAL INPUTS TOWHICH INFORMATION REPRESENTING SIGNALS MAY BE APPLIED FOR SETTING THEELEMENTS TO FIRST OR SECOND BINARY INFORMATION REPRESENTING STATES, EACHSAID ELEMENT HAVING TRUE AND COMPLEMENT OUTPUTS OPERABLE TO SUPPLYOUTPUT SIGNALS REPRESENTING RESPECTIVELY THE BINARY INFORMATION STATE TOWHICH THE ELEMENT IS SET AND THE BINARY COMPLEMENT OF THAT STATE,COMPRISING: SIGNAL GENERATING MEANS FOR PROVIDING TEST SIGNALS INCLUDINGAT LEAST ONE INQUIRY WORD HAVING A NUMBER OF BITS EQUAL TO THE NUMBER OFELEMENTS IN THE DEVICE AND A RESPONSE WORD WHICH IS THE BINARYCOMPLEMENT OF THE CORRESPONDING INQUIRY WORD; MEANS FOR CONNECTING THESIGNAL GENERATING MEANS TO THE INPUTS OF SAID DEVICE; REGISTER MEANSCONNECTED TO RECEIVE THE SIGNALS PROVIDED BY THE COMPLEMENT OUTPUTS OFTHE ELEMENTS AND TO PROVIDE OUTPUT SIGNALS WHICH ARE THE BINARYEQUIVALENT THEREOF; AND BIT-FOR-BIT COMPARING AND INDICATING MEANSOPERABLY CONNECTED TO THE TRUE OUTPUTS OF THE ELEMENTS OF THE DEVICE ANDTHE OUTPUTS OF THE REGISTER MEANS FOR COMPARING CORRESPONDING POSITIONSOF THE SAID TWO OUTPUTS AND INDICATING THOSE POSITIONS HAVING DIFFERINGBINARY STATES.